1. Field of the Invention
The present invention relates to an extended logical scale structure of a programmable logical array, and more particularly to an extended logical scale structure of a programmable logic array which makes it possible to extend the scale of a logic circuit formed by a single logic array to a scale equivalent to the scale of a logic circuit formed by a plurality of logic arrays.
2. Description of the Related Art
A programmable logic array (hereinafter simply referred to as a PLA) is hardware for a logical calculation which can achieve a programmable logic circuit, and is a logic operation circuit which can present a desired logic circuit by a simple structure and which execute logic operation at high speeds.
FIG. 1 shows a basic structure of a PLA. For the sake of simplicity, FIG. 1 illustrates a PLA which achieves a logic operation circuit having two inputs (x.sub.1, x.sub.2) and two outputs (y.sub.1, y.sub.2). An input x.sub.1 is supplied to an input buffer 11.sub.1. A positive logic output x.sub.1 of the input buffer 11.sub.1 is output to an input line 1.sub.1, and a negative logic output x.sub.1 thereof is output to an input line 1.sub.2. Similarly, an input is supplied to an input buffer 11.sub.2. A positive logic output x.sub.2 of the input buffer 11.sub.2 is output to an input line 1.sub.3, and a negative logic output x.sub.2 thereof is output to an input line 1.sub.4.
Resistors 12.sub.1 and 12.sub.2 each having an end connected to ground are connected to input terminals of output buffers 13.sub.1 and 13.sub.2 through output lines O.sub.1 and O.sub.2, respectively. Product term lines a.sub.1 and a.sub.2 extend in the direction perpendicular to the input lines 1.sub.1 -1.sub.4 and the output lines O.sub.1 and O.sub.2. The product term lines a.sub.1 and a.sub.2 are supplied with a high-level voltage Vcc through resistors 14.sub.1 and 14.sub.2, respectively.
Intersecting points where the input lines 1.sub.1 -1.sub.4 and the output lines O.sub.1 and O.sub.2 intersect with the product term lines a.sub.1 and a.sub.2 are called PLA intersecting points 15. A wiring group of the input lines 1.sub.1 -1.sub.4 and the product term lines a.sub.1 and a.sub.2 is called an AND array 16. A wiring group of the output lines O.sub.1 and O.sub.2 and the product term lines a.sub.1 and a.sub.2 is called an OR array 17.
The inputs x.sub.1 and x.sub.2 are drawn through the output buffers 13.sub.1 and 13.sub.2 as the outputs y.sub.1 and y.sub.2, which are represented by a logic formula of a desired sum-of-products style by making related groups of the PLA intersecting points 15 closed or open.
Now, a case is considered where hatched intersecting points among the PLA intersecting points 15 shown in FIG. 1 are made closed (short-circuits). In this case, the product term line a.sub.1 is logic 1 when both the logic x.sub.1 of the input line 1.sub.1 and the logic x.sub.2 of the input line 1.sub.4 are logic 1. The product term line a.sub.2 is logic 1 when both the logic x.sub.1 of the input one 1.sub.2 and the logic x.sub.2 of the input line 1.sub.3 are logic 1. When the output line O.sub.1 is logic 1 when at least one of the product lines a.sub.1 and a.sub.2 is logic 1. When the output line O.sub.2 is logic 1 when the product term line a.sub.1 is logic 1. Therefore, the logical relationship between the outputs y.sub.1, y.sub.2 and the inputs x.sub.1, x.sub.2 are as follows: EQU y.sub.1 =x.sub.1 .multidot.x.sub.2 +x.sub.1 .multidot.x.sub.2 EQU y.sub.2 =x.sub.1 .multidot.x.sub.2 .multidot.
In a similar manner to the above-mentioned manner, a desired logic circuit can be formed by making a decision on whether each of the PLA intersecting points 15 should be made closed or open.
Conventionally, each of the PLA intersecting points 15 shown in FIG. 1 is formed by use of a fuse 18 shown in FIG. 2. In this case, all the fuses 18 corresponding the PLA intersecting points 15 are short-circuits at the stage of production. When a user uses PLA, a current pulse is applied to some of the fuses 18 selected based on the contents of a program achieved by a desired logic circuit. Thereby, the unnecessary fuses 18 at the PLA intersecting points 15 are made open so that desired configurations of the AND array 16 and the OR array 17 can be obtained. A PLA which has not been programmed at the manufacturing stage and which is programmed when used by users, is called a field programmable logic array (hereinafter simply referred to an FPLA).
However, in the above-mentioned fusing type FPLA, the fuses 18 must be fused by a specific fusing device in order to form a desired logic circuit. For this reason, programming is freely possible only before the user mounts the FPLA on a user's device. Further, the programmed contents cannot be modified after fusing.
In order to compensate the above-mentioned disadvantages, another PLA has been proposed in which the fuse 18 is replaced by a semiconductor switching element 19 shown in FIG. 3. The proposed PLA is an FPLA which provides a desired logic circuit by controlling the semiconductor switching element 19 through a control line 20 shown in FIG. 3 on the basis of ON/OFF information (hereinafter referred to as intersecting point information also) stored in a memory element. Such an FPLA is called an electrically alterable programmable logic array (hereinafter simply referred to as an EAPLA).
In such an EAPLA, it is possible to repeatedly program and modify the contents of logic since it does not utilize the structure that the fuse 18 is physically fused. In the EAPLA, pieces of intersecting point information equal to the number of the PLA intersecting points 15 forming the PLA are stored in the memory element. Each time logic of the PLA is changed, the storage contents of the memory element are changed. With the above-mentioned structure, a plurality of logic circuits can be achieved by a single EAPLA.
However, in the above-mentioned EAPLA, the scale of logic circuit is based on the number of semiconductor switching elements 19 equal to the number of the PLA intersecting points 15. For this reason, the degree of freedom to design logic circuits is low. Further, a structure of large size is required to achieve complex logic operation and a variety of logic operations.
In the case where a logic circuit is configured by use of PLA and the configured logic circuit is debugged by use of outputs of the logic circuit, it is required to use a large number of PLAs.
Moreover, in the case where the contents of the logic circuit are modified by changing intersecting point information on the semiconductor switching elements 19 of the PLA intersecting points, it is impossible to check whether a desired modification of logic has been provided in the logic circuit.
The present invention was made taking into account the above-mentioned matters, and is directed to providing an extended logical scale structure of a programmable logic array which makes it possible to extend the scale of a logic circuit formed by a single logic array to a scale equivalent to the scale of a logic circuit formed by a plurality of logic arrays.